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upi semiconductor corp., http://www.upi-semi.com rev. f00, file name: up6103-ds-f0000 up6103 1 5v/12v synchronous-rectified buck controller with reference input the up6103 is a compact synchronous-rectified buck controller specifically designed to operate from 5v or 12v supply voltage and to deliver high quality output voltage as low as 0.4v. these sop-8 and psop-8 devices operate at fixed 200/300 khz frequency and provide an optimal level of integration to reduce size and cost of the power supply. the up6103 supports both tracking mode and stand-alone mode operation. the output voltage is tightly regulated to the external reference voltage from 0.4v to 3.0v at tracking mode or to internal 0.6v reference at stand-alone mode. this controller integrates internal mosfet drivers that support 12v+12v bootstrapped voltage for high efficiency power conversion. the bootstrap diode is built-in to simplify the circuit design and minimize external part count. other features include internal softstart, undervoltage protection, overcurrent protection and shutdown function. with aforementioned functions, this part provides customers a compact, high efficiency, well-protected and cost-effective solutions. this part is available in sop-8 and psop-8 packages. ? ? ? ? ? operate from 5v or 12v supply voltage ? ? ? ? ? 3.3v to 12v v in input range ? ? ? ? ? 0.6 v ref with 1.5% accuracy ? ? ? ? ? output range from v ref to 80% of v in ? ? ? ? ? support tracking mode and stand alone mode operation ? ? ? ? ? simple single-loop control design ? ? ? ? ? voltage-mode pwm control ? ? ? ? ? fast transient response ? ? ? ? ? high-bandwidth error amplifier ? ? ? ? ? 0% to 80% duty cycle ? ? ? ? ? lossless, programmable overcurrent protection ? ? ? ? ? uses lower mosfet r ds(on) ? ? ? ? ? 200/300 khz fixed frequency oscillator ? ? ? ? ? internal soft start ? ? ? ? ? integrated bootstrap diode ? ? ? ? ? rohs compliant and halogen free r e b m u n r e d r oe g a k c a pg n i k r a m p o tk r a m e r 8 s 3 0 1 6 p ul 8 - p o s8 s 3 0 1 6 p uz h k 0 0 2 8 s a 3 0 1 6 p ul 8 - p o s8 s a 3 0 1 6 p uz h k 0 0 3 8 u s a 3 0 1 6 p ul 8 - p o s p8 u s a 3 0 1 6 p uz h k 0 0 3 ? ? ? ? ? power supplies for microprocessors or subsystem power supplies ? ? ? ? ? cable modems, set top boxes, and xdsl modems ? ? ? ? ? industrial power supplies; general purpose supplies ? ? ? ? ? 5v or 12v input dc-dc regulators ? ? ? ? ? low voltage distributed power supplies 8 up6103 4 1 3 6 7 2 boot ugate gnd lgate phase refin fb vcc 5 enable disable reference input v in v out option general description a pplications ordering information features pin configuration & typical application circuit note: upi products are compatible with the current ipc/ jedec j-std-020 requirements. they are halogen-free, rohs compliant and 100% matte tin (sn) plating that are suitable for use in snpb or pb-free soldering processes. phase boot refin fb vcc ugate gnd lgate 1 2 3 45 6 7 8 psop-8 gnd phase boot refin fb vcc ugate gnd lgate 1 2 3 45 6 7 8 sop-8
upi semiconductor corp., http://www.upi-semi.com rev. f00, file name: up6103-ds-f0000 up6103 2 . o ne m a n n i pn o i t c n u f n i p 1t o o b y l p p u s p a r t s t o o b c r o t i c a p a c p a r t s t o o b e h t t c e n n o c . r e v i r d e t a g r e p p u g n i t a o l f e h t r o f t o o b r o t i c a p a c p a r t s t o o b e h t . t i u c r i c p a r t s t o o b a m r o f o t n i p e s a h p e h t d n a n i p t o o b n e e w t e b r o f s e u l a v l a c i p y t . t e f s o m r e p p u e h t n o n r u t o t e g r a h c e h t s e d i v o r pc t o o b o t f u 1 . 0 m o r f e g n a r c t a h t e r u s n e . f u 7 4 . 0 t o o b . c i e h t r a e n d e c a l p s i 2e t a g u . t u p t u o r e v i r d e t a g r e p p u d e r o t i n o m s i n i p s i h t . t e f s o m r e p p u f o e t a g e h t o t n i p s i h t t c e n n o c s a h t e f s o m r e p p u e h t n e h w e n i m r e t e d o t y r t i u c r i c n o i t c e t o r p h g u o r h t - t o o h s e v i t p a d a e h t y b . f f o d e n r u t 3d n g . c i e h t r o f d n u o r g r e w o p d n a l a n g i s . n i p s i h t o t t c e p s e r h t i w d e r u s a e m e r a s l e v e l s e g a t l o v l l a . e l b a l i a v a n o i t c e n n o c e c n a d e p m i t s e w o l e h t h g u o r h t e n a l p / d n a l s i d n u o r g e h t o t n i p s i h t e i t 4e t a g l . t u p t u o r e v i r d e t a g r e w o l d e r o t i n o m s i n i p s i h t . t e f s o m r e w o l f o e t a g e h t o t n i p s i h t t c e n n o c n r u t s a h t e f s o m r e w o l e h t n e h w e n i m r e t e d o t y r t i u c r i c n o i t c e t o r p h g u o r h t - t o o h s e v i t p a d a e h t y b . f f o 5c c v . e g a t l o v y l p p u s e h t . r e v i r d e t a g r e w o l e h t d n a 3 0 1 6 p u e h t r o f y l p p u s s a i b e h t s e d i v o r p n i p s i h t d e l p u o c e d - l l e w a t c e n n o c . t i u c r i c l o r t n o c l a n r e t n i r o f d d v 4 o t d e t a l u g e r y l l a n r e t n i s i e g a t l o v y l p p u s e h t r a e n d e c a l p s i r o t i c a p a c g n i l p u o c e d a t a h t e r u s n e . n i p s i h t o t e g a t l o v y l p p u s v 2 . 3 1 o t v 5 . 4 . c i 6b f . e g a t l o v k c a b d e e f m o r f r e d i v i d r o t s i s e r a . r e i f i l p m a r o r r e e h t o t t u p n i g n i t r e v n i e h t s i n i p s i h t e h t h t i w n o i t a n i b m o c n i n i p s i h t e s u . e g a t l o v n o i t a l u g e r e h t t e s o t d e s u s i d n g o t t u p t u o e h t . r e t r e v n o c e h t f o p o o l k c a b d e e f l o r t n o c e g a t l o v e h t e t a s n e p m o c o t n i p n e / p m o c 7n i f e r . n o i t a r e p o e d o m g n i k c a r t r o f t u p n i e c n e r e f e r l a n r e t x e h t i w e g a t l o v a s e v i e c e r n i p s i h t . r e i f i l p m a r o r r e e h t f o t u p n i g n i t r e v n i - n o n e h t t a e g a t l o v e c n e r e f e r e h t s a v 0 . 3 o t v 4 . 0 m o r f e g n a r e h t , p o t s o t r o t a l l i c s o e h t s e s u a c d n a r e l l o r t n o c e h t s e l b a s i d v 3 . 0 n a h t r e w o l n i p s i h t g n i l l u p . e s u e c n e r e f e r v 6 . 0 l a n r e t n i r o f n e p o n i p s i h t t e l . w o l d l e h e b o t s t u p t u o e t a g l d n a e t a g u 8e s a h p . e d o n h c t i w s e s a h p f o n i a r d e h t d n a t e f s o m r e p p u e h t f o e c r u o s e h t o t n i p s i h t t c e n n o c e g a t l o v e h t r o t i n o m o t d n a , r e v i r d e t a g u e h t r o f k n i s e h t s a d e s u s i n i p s i h t . t e f s o m r e w o l e h t e h t y b d e r o t i n o m o s l a s i n i p s i h t . n o i t c e t o r p t n e r r u c r e v o r o f t e f s o m r e w o l e h t s s o r c a p o r d . f f o d e n r u t s a h t e f s o m r e p p u e h t n e h w e n i m r e t e d o t y r t i u c r i c n o i t c e t o r p h g u o r h t - t o o h s e v i t p a d a t n e i s n a r t e v i t a g e n e c u d e r o t d e d n e m m o c e r s i d n u o r g d n a n i p s i h t n e e w t e b e d o i d y k t t o h c s a . m e t s y s y l p p u s r e w o p a n i n o m m o c s i h c i h w e g a t l o v d a p d e s o p x e . e g a k c a p 8 - p o s p r o f t a e h e v i t c e f f e r o f b c p o t d e r e d l o s l l e w e b d l u o h s d a p d e s o p x e e h t . d n u o r g e h t d a p d e s o p x e e h t t c e n n o c . n o i t c u d n o c functional pin descriptio n
upi semiconductor corp., http://www.upi-semi.com rev. f00, file name: up6103-ds-f0000 up6103 3 enable 0.3v pwm vcc amplifier error 0.6v vcc gnd lgate phase ugate boot fb refin v ocp 4vdd 7 6 reference selection oscillator soft start por gate control logic 4 8 internal regulator 2 1 5 3 ocp comparator v ref ss functional block diagram
upi semiconductor corp., http://www.upi-semi.com rev. f00, file name: up6103-ds-f0000 up6103 4 the up6103 is a compact synchronous-rectified buck controller specifically designed to operate from 5v or 12v supply voltage and to deliver high quality output voltage as low as 0.4v. these sop-8 and psop-8 devices operate at fixed 200/300 khz frequency and provide an optimal level of integration to reduce size and cost of the power supply. the up6103 supports both tracking mode and stand-alone mode operation. the output voltage is tightly regulated to the external reference voltage from 0.4v to 3.0v at tracking mode or to internal 0.6v reference at stand-alone mode. supply voltage the vcc pin receives a well-decoupled 4.5v to 13.2v supply voltage to power the up6103 control circuit, the lower gate driver and the bootstrap circuit for the higher gate driver. a minimum 0.1uf ceramic capacitor is recommended to bypass the supply voltage. place the bypassing capacitor physically near the ic. an internal linear regulator regulates supply voltage into a 4.5v voltage 4.5vdd for internal control logic circuit. no external bypass capacitor is required for filtering the 4.5vdd voltage. the up6103 integrates mosfet gate drives that are powered from the vcc pin and support 12v+12v driving capability. a bootstrap diode is embedded to facilitates pcb design and reduce the total bom cost. no external schottky diode is required. converters that consist of up6103 feature high efficiency without special consideration on the selection of mosfets. note: the embedded bootstrap diode is not a schottky diode having a 0.7v forward voltage. external schottky diode is highly recommended if the vcc voltage is expected to be lower than 5.0v. otherwise the bootstrap diode may be too low for the device to work normally. power on reset and chip enable a power on reset (por) circuitry continuously monitors the supply voltage at vcc pin. once the rising por threshold is exceeded, the up6103 sets itself to active state and is ready to accept chip enable command. the rising por threshold is typically 4.2v at vcc rising. the refin is a multifunctional pin: external reference input and chip enable as shown in figure 1. to select internal 0.6v reference voltage , just let the refin open. a 100ua current source tries to pull high the refin voltage after por that is monitored by the enable comparator monitors for chip enable. a signal level transistor is adequate to pull this pin down to ground and shut down the up6103. as q1 is turned off, the refin voltage is pulled high to 3.3vdd by the 100ua current source. as the refin voltage acrosses 0.3v threshold level, the enable comparator initiates the operation of the up6103. the refin voltage is compared with 3.0v voltage to select the reference voltage with 1ms time delay after chip enabling. the internal 0.6v reference voltage is selected as the refin pulled high to internal 3.3vdd. the softstart cycle is initiated after reference selection is completed. to select external reference voltage, connect refin to a voltage source range from 0.4v to 3v. as q1 is turn off, the refin voltage is aligned to the external reference input. as the refin voltage acrosses 0.3v threshold level, the enable comparator initiates the operation of the up6103. the refin voltage is compared with 3.0v voltage to select the reference voltage with 1ms time delay after chip enabling. the external reference input is selected as the refin voltage is lower than 3.0v. the 100ua current source is turn off if the external reference input is select to eliminate the load effect on the reference input. the softstart cycle is initiated after reference selection is completed. note that the 100ua current source will induces load effect on the external reference input and causes the refin voltage slightly higher than the external reference input during the reference selection. make sure that the external reference input is strong enough so that refin voltage will not be higher than 3.0v. chip enable 0.3v v ref (0.6v) refin 7 reference selection 4.5vdd 1ms delay reference voltage enable disable reference input up6103 100ua 3.0v q1 figure 1. chip enable and reference selection function softstart a built-in soft start is used to prevent surge current from power supply input during turn on (referring to the functional block diagram). the error amplifier is a three-input device. reference voltage v ref or the internal soft start voltage ss whichever is smaller dominates the behavior of the non- inverting input of the error amplifier. ss internally ramps up functional description
upi semiconductor corp., http://www.upi-semi.com rev. f00, file name: up6103-ds-f0000 up6103 5 to 5vdd in 66ms after the softstart cycle is intiated (for up6103). the ramp is created digitally, so there will be 100 small discrete steps. accordingly, the output voltage will follow the ss signal and ramp up smoothly to its target level. the ss signal keeps ramping up after it execeeds the internal reference v ref . however, the reference voltage v ref takes over the behavior of error amplifier after ss > v ref . when the ss signal climb to its ceiling voltage (5v), the up6103 claims the end of softstart cyclce and enable the under voltage protection of the output voltage. for internal reference voltage, the effective ramp-up time of the output voltage is about 3.6ms. for external reference voltage, the effective ramp up time output voltage is calculated as: ref ss v 6 t = (ms) figure 2 shows a typical start up interval where the refin pin has been released from a grounded (system shutdown) state. v in 5v/div v out 0.5v/div lgate 5v/div i x 2.5/div 2ms/div figure 2. softstart behavior. power input detection the up6103 detects phase voltage for the present of power input when the ugate turns on the first time. if the phase voltage does not exceed 3.0v when the ugate turns on, the up6103 asserts that power input in not ready and stops the softstart cycle. however, the internal ss continues ramping up to 5vdd. another softstart is initiated after ss ramps up to 5vdd. the hiccup period is about 12ms. figure 3 shows the start up interval where v in does not present initially. switching frequency the switching frequency is fixed and can not be changed externally. typical switching frequency is 200khz for up6103, 300khz for up6103a. higher switching frequncy allows higher control bandwidth and faster transient response. however higher swithcing frequency results in higher power loss in both controller and power mosfets. the up6103 detects phase voltage for the existence of power input when the ugate turns on the first time. if the phase voltage does not exceed 3.0v when the ugate turns on, the up6103 asserts that power input in not ready and stops the softstart cycle. however, the internal ss continues ramping up to 3.3vdd. another softstart is initiated after ss ramps up to 3.3vdd. the hiccup period is about 6.4ms. figure 3 shows the start up interval where v in does not present initially. lgate 5v/div v in 5v/div v out 5v/div 1ms/div figure 3. softstart where vin does not present initially. overcurrent protection (ocp) the up6103 detects voltage drop across the lower mosfet (v phase ) for overcurrent protection when it is turn on. if v phase is lower than v ocp = -375mv, the up6103 asserts ocp and shuts down the converter. another factor should taken into consideration is the ripple of the inductor current. the current near the valley of the ripple current is used for ocp, resulting the averaged ocp level a little higher than the calculated value. undervoltage protection (uvp) the fb voltage is monitored for undervoltage protection. the uvp threshold level is typical 0.4v for both stand- alone and tracking mode. the up6103 shuts down upon the detection of uvp and can be reset only by por or toggling refin pin. functional description
upi semiconductor corp., http://www.upi-semi.com rev. f00, file name: up6103-ds-f0000 up6103 6 package thermal resistance (note 3) sop-8 ja ------------------------------------------------------------------------------------------------------------------------------- --- 160 c/w sop-8 jc ------------------------------------------------------------------------------------------------------------------------------ ----- 39 c/w psop-8 ja ------------------------------------------------------------------------------------------------------------------------------- --- 50 c/w psop-8 jc ------------------------------------------------------------------------------------------------------------------------------- ----- 5 c/w power dissipation, p d @ t a = 25 c sop-8 ------------------------------------------------------------------------------------------------------------------------- ------------------ 0.625w psop-8 ------------------------------------------------------------------------------------------------------------------------ ------------------------- 2w operating junction temperature range (note 4) ------------------------------------------------------------------------ -40 c to +125 c operating ambient temperature ra nge -------------------------------------------------------------------------------------- -40 c to +85 c supply input voltage, v cc ---------------------------------------------------------------------------------------------------------------- +4.5v to 13.2v r e t e m a r a pl o b m y ss n o i t i d n o c t s e tn i mp y tx a ms t i n u t u p n i y l p p u s e g a t l o v y l p p u sv c c 5 . 4- -2 . 3 1v t n e r r u c y l p p u si c c v ; n e p o e t a g l , e t a g u c c g n i h c t i w s , v 2 1 =- -3- -a m t n e r r u c y l p p u s t n e c s e i u qi q _ c c v b f g n i h c t i w s o n , v 7 . 0 =- -2- -a m e g a t l o v t u p n i r e w o pv n i 0 . 3- -2 . 3 1v t e s e r n o r e w o p d l o h s e r h t r o pv h t r c c v c c g n i s i r0 . 42 . 44 . 4v s i s e r e t s y h r o pv s y h c c - -5 . 0- -v (v cc = 12v, t a = 25 o c, unless otherwise specified) a bsolute maximum ratin g thermal informatio n recommended operation conditions electrical characteristics supply input voltage, vcc (note 1) ------------------------------------------------------------------------------------------------ -0.3v to +15v phase to gnd dc ---------------------------------------------------------------------------------------------------------------------------- --------- -5v to 15v < 200ns ----------------------------------------------------------------------------------------------------------------------- ----- -10v to 30v boot to gnd dc ------------------------------------------------------------------------------------------------------------------------- -0 .3v to phase +15v < 200ns ----------------------------------------------------------------------------------------------------------------------- --- -0.3v to 42v lgate to gnd dc ---------------------------------------------------------------------------------------------------------------------------- --------- -1v to 15v < 200ns ----------------------------------------------------------------------------------------------------------------------- ----- -5v to 30v ugate to phase dc ---------------------------------------------------------------------------------------------------------------------------- --------- -0.3v to 15v < 200ns ----------------------------------------------------------------------------------------------------------------------- ----- -2v to 20v input, output or i/o voltage -------------------------------------------------------------------------------------------------- -------- -0.3v to +6v storage temperature range ------------------------------------------------------------------------------------------------------------- -65 o c to +150 o c junction temperature ------------------------------------------------------------------------------------------------------------------------------- ----- 150 o c lead temperature (soldering, 10 sec) ------------------------------------------------------------------------------------------------------------ 260 o c esd rating (note 2) hbm (human body mode) --------------------------------------------------------------------------------------------------------------------- 2kv mm (machine mode) ----------------------------------------------------------------------------------------------------------------------------- 2 00v
upi semiconductor corp., http://www.upi-semi.com rev. f00, file name: up6103-ds-f0000 up6103 7 note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 4. the device is not guaranteed to function outside its operating conditions. r e t e m a r a pl o b m y ss n o i t i d n o c t s e tn i mp y tx a ms t i n u r o t a l l i c s o y c n e u q e r f g n i n n u r e e r ff c s o 3 0 1 6 p u0 7 10 0 20 3 2z h k a 3 0 1 6 p u5 5 20 0 35 4 3z h k e d u t i l p m a p m a r ? v c s o v c c v 2 1 =- -0 . 1- -v p - p r e i f i l p m a r o r r e n i a g c d p o o l n e p oo an g i s e d y b d e e t n a r a u g5 50 7- -b d t c u d o r p h t d i w d n a b - n i a gw b gn g i s e d y b d e e t n a r a u g- -0 1- -z h m e t a r w e l sr sn g i s e d y b d e e t n a r a u g36- -s u / v e c n a t c u d n o c s n a r tn g i s e d y b d e e t n a r a u g- -- -7 . 0s m s r e v i r d e t a g r e l l o r t n o c m w p t n e r r u c g n i c r u o s e t a g r e p p ui c r s _ g u v t o o b v - e s a h p v , v 2 1 = t o o b v - e t a g u v 6 =- -1 -- -a t n e r r u c g n i k n i s e t a g r e p p ui k n s _ g u v t o o b v - e s a h p v , v 2 1 = e t a g u v - e s a h p v 6 =- -5 . 1- -a r e t a g r e p p u ) n o ( s d g n i k n i sr k n s _ g u v e t a g u v - e s a h p v 1 . 0 =- -24 ? t n e r r u c g n i c r u o s e t a g r e w o li c r s _ g l v c c v - e t a g l v 6 =- -1 -- -a t n e r r u c g n i k n i s e t a g r e w o li k n s _ g l v e t a g l v 6 =- -2- -a r e t a g r e w o l ) n o ( s d g n i k n i sr k n s _ g l v e t a g l v 1 . 0 =- -24 ? e t a g l o t g n i l l a f e s a h p y a l e d g n i s i r v c c v ; v 2 1 = e s a h p v o t v 2 . 1 < e t a g l v 2 . 1 >- -0 30 9s n e t a g u o t g n i l l a f e t a g l y a l e d g n i s i r v c c v ; v 2 1 = e t a g l v ( o t v 2 . 1 < e t a g u v - e s a h p > ) v 2 . 1 - -0 30 9s n e g a t l o v e c n e r e f e r e g a t l o v k c a b d e e f l a n i m o nv b f e d o m e n o l a d n a t s1 9 5 . 06 . 09 0 6 . 0v y c a r u c c a e g a t l o v t u p t u o v | b f v - n i f e r v , | n i f e r g n i k c a r t , v 0 . 1 ~ v 4 . 0 = e d o m - -- -5 1v m v | b f v - n i f e r v / | n i f e r v , n i f e r , v 0 . 3 ~ v 0 . 1 = e d o m g n i k c a r t - -- -5 . 1% d l o h s e r h t e l b a n e n i f e rv n i f e r - -3 . 05 3 . 0v n o i t c e t o r p n o i t c e t o r p e g a t l o v r e d n uv p v u _ b f 3 . 04 . 05 . 0v d l o h s e r h t t n e r r u c r e v ov e s a h p r e t a g l n e p o- -5 7 3 -- -v m l a v r e t n i t r a t s - t f o st s s e d o m e n o l a d n a t s4 . 26 . 38 . 4s m electrical characteristics
upi semiconductor corp., http://www.upi-semi.com rev. f00, file name: up6103-ds-f0000 up6103 8 refin 0.5v/div v out 0.5v/div lgate 5v/div ugate - phase 5v/div phase 5v/div ugate 5v/div lgate 5v/div switching waveforms: ugate trun off 25ns/div v in = 12v, i out = 10a ugate - phase 5v/div phase 5v/div ugate 5v/div lgate 5v/div refin 5v/div v out 0.5v/div lgate 10v/div i x 10a/div v in 5v/div v out 0.5v/div lgate 5v/div i x 2.5/div refin 2v/div v out 0.5v/div lgate 5v/div i x 2.5a/div typical operation characteristics refin operation 10ms/div v in = 12v, c out = 1500uf, i out = 6a power on waveforms 2ms/div v in =12v, v out = 1.2v, c out = 1500uf, no load turn on from refin 2ms/div v in =12v, v out = 1.2v, c out = 1500uf, no load turn off from refin 10us/div v in = 12v, v out = 1.2v, c out = 1500uf, i out = 6a switching waveforms: ugate turn on 25ns/div v in = 12v, i out = 10a
upi semiconductor corp., http://www.upi-semi.com rev. f00, file name: up6103-ds-f0000 up6103 9 v out 0.5v/div phase 5v/div i x 20a/div v out 0.5v/div phase 5v/div i x 20a/div i out 10a/div phase 10v/div v out 5v/div lgate 5v/div v in 5v/div v out 5v/div typical operation characteristics power sequencing operation 1ms/div v cc =12v ready, v out = 1.2v, c out = 1500uf, no load load transient response 10us/div v in =12v, v out = 1.2v, c out = 1500uf over current protection 5ms/div, v in = 12v, v out = 1.2v, c out = 1500uf, output short to ground over current protection 5ms/div, v in = 12v, v out = 1.2v, c out = 1500uf, turn on to short circuit load regulation output current (a) output voltage deviation (%) line regulation input voltage (v) output voltage deviation (%) -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0 5 10 15 20 25 30 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 4 6 8 101214
upi semiconductor corp., http://www.upi-semi.com rev. f00, file name: up6103-ds-f0000 up6103 10 switching frequency vs. input voltage input voltage (v) switching frequency (khz) typical operation characteristics 175 180 185 190 195 200 205 210 215 220 225 468101214 output voltage vs. junction temperature junction temperature ( o c) output voltage varition (%) -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 -50 -25 0 25 50 75 100 125 175 180 185 190 195 200 205 210 215 220 225 -50 -25 0 25 50 75 100 125 switching frequency vs. junction temperature junction temperature ( o c) switching frequency (khz)
upi semiconductor corp., http://www.upi-semi.com rev. f00, file name: up6103-ds-f0000 up6103 11 power mosfet selection external component selection is primarily determined by the maximum load current and begins with the selection of power mosfet switches. the up6103 requires two external n-channel power mosfets for upper (controlled) and lower (synchronous) switches. important parameters for the power mosfets are the breakdown voltage v (br)dss , on-resistance r ds(on) , reverse transfer capacitance c rss , maximum current i ds(max) , gate supply requirements, and thermal management requirements. the gate drive voltage is powered by vcc pin that receives 4.5v~13.2v supply voltage. when operating with a 12v power supply for vcc (or down to a minimum supply voltage of 8v), a wide variety of nmosfets can be used. logic-level threshold mosfet should be used if the input voltage is expected to drop below 8v. since the lower mosfet is used as the current sensing element, particular attention must be paid to its on-resistance. look for r ds(on) ratings at lowest gate driving voltage. special cautions should be exercised on the lower switch exhibiting very low threshold voltage v gs(th) . the shoot- through protection present aboard the up6103 may be circumvented by these mosfets if they have large parasitic impedences and/or capacitances that would inhibit the gate of the mosfet from being discharged below its threshold level before the complementary mosfet is turned on. also avoid mosfets with excessive switching times; the circuitry is expecting transitions to occur in under 50 nsec or so. in high-current applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss components; conduction loss and switching loss. the conduction losses are the largest component of power dissipation for both the upper and the lower mosfets. these losses are distributed between the two mosfets according to duty cycle. since the up6103 is operating in continuous conduction mode, the duty cycles for the mosfets are: in out up v v d = ; in out in lo v v v d ? = the resulting power dissipation in the mosfets at maximum output current are: osc sw in out up ) on ( ds 2 out up f t v i 5 . 0 d r i p + = lo ) on ( ds 2 out lo d r i p = where t sw is the combined switch on and off time. a pplication information both mosfets have i 2 r losses and the top mosfet includes an additional term for switching losses, which are largest at high input voltages. the bottom mosfet losses are greatest when the bottom duty cycle is near 100%, during a short-circuit or at high input voltage. these equations assume linear voltage current transitions and do not adequately model power loss due the reverse-recovery of the lower mosfet?s body diode. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air flow. the gate-charge losses are dissipated by the up6103 and don?t heat the mosfets. however, large gate charge increases the switching interval, t sw that increases the mosfet switching losses. the gate-charge losses are calculated as: osc rss in lo _ iss up _ iss cc cc g f ) c v ) c c ( v ( v p + + = where c iss_up is the input capacitance of the upper mosfet, c iss_lo is the input capacitance of the lower mosfet, and c rss_up is the reverse transfer capacitance of the upper mosfet. make sure that the gate-charge loss will not cause over temperature at up6103, especially with large gate capacitance and high supply voltage. output inductor selection output inductor selection usually is based the considerations of inductance, rated current, size requirement, and dc resistance (dc) given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: ) v v 1 ( v l f 1 i in out out out osc l ? = ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. highest efficiency operation is obtained at low frequency with small ripple current. however, achieving this requires a large inductor. there is a tradeoff between component size, efficiency and operating frequency. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . there is another tradeoff between output ripple current/ voltage and response time to a transient load. increasing the value of inductance reduces the output ripple current and voltage. however, the large inductance values reduce the converter?s re sponse time to a load transient.
upi semiconductor corp., http://www.upi-semi.com rev. f00, file name: up6103-ds-f0000 up6103 12 a pplication information maximum current ratings of the inductor are generally specified in two methods: permissible dc current and saturation current. permissible dc current is the allowable dc current that causes 40 o c temperature raise. the saturation current is the allowable current that causes 10% inductance loss. make sure that the inductor will not saturate over the operation conditions including temperature range, input voltage range, and maximum output current. the size requirements refer to the area and height requirement for a particular design. for better efficiency, choose a low dc resistance inductor. dcr is usually inversely proportional to size. different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and don?t radi ate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. the choice of which style inductor to use often depends more on the price vs. size requirements and any radiated field/emi requirements. input capacitor selection the synchronous-rectified buck converter draws pulsed current with sharp edges from the input capacitor resulting in ripples and spikes at the input supply voltage. use a mix of input bypass capacitors to control the voltage overshoot across the mosfets. use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time upper mosfet turns on. place the small ceramic capacitors physically close to the mosfets and between the drain of upper moset and the source of lower mosfet to avoid the stray inductance along the connection trace. the important parameters for the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. the rms current rating requirement for the input capacitor of a buck converter is calculated as: in out in out ) max ( out ) rms ( in v ) v v ( v i i ? = this formula has a maximum at v in = 2v out , where i in(rms) = i out(rms) /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that the capacitor manufactur er?s ri pple current ratings are often based on 2000 hours of life. this makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. always consult the manufacturer if there is any question. for a through-hole design, several electrolytic capacitors may be needed. for surface mount designs, solid tantalum capacitors can also be used, but caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of handling the surge-current at power-up. some capacitor series available from reputable manufacturers are surge current tested. output capacitor selection an output capacitor is required to filter the output and supply the load transient current. the selection of c out is primarily determined by the esr required to minimize voltage ripple and load step transients. the output ripple ? v out is approximately bounded by: ) c f 8 1 esr ( i v out osc l out + ? ? since ? il increases with input voltage, the output ripple is highest at maximum input voltage. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering and has the necessary rms current rating. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. the load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. these requirements are generally met with a mix of capacitors and careful layout. modern components and loads are capable of producing transient load rates above 1a/ns. high frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements.
upi semiconductor corp., http://www.upi-semi.com rev. f00, file name: up6103-ds-f0000 up6103 13 a pplication information use only specialized low-esr capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitor?s esr will determine the output ri pple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electrolytic capa citor?s esr value is related to the case size with lower esr available in larger case sizes. however, the equivalent series inductance (esl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. unfortunately, esl is not a specified parameter. work with your capacitor supplier and measure the capa citor?s impedance with frequency to select a suitable component. in most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. bootstrap capacitor selection an external bootstrap capacitor c boot connected to the boot pin supplies the gate drive voltage for the upper mosfet. this capacitor is charged through the internal diode when the phase node is low. when the upper mosfet turns on, the phase node rises to v in and the boot pin rises to approximately v in + v cc . the boot capacitor needs to store about 100 times the gate charge required by the upper mosfet. in most applications 0.1uf to 0.47uf, x5r or x7r dielectric capacitor is adequate. pcb layout considerations high speed switching and relatively large peak currents in a synchronous-rectified buck converter make the pcb layout a very important part of design. fast current switching from one device to another in a synchronous-rectified buck converter causes voltage spikes across the interconnecting impedances and parasitic circuit elements. the voltage spikes can degrade efficiency and radiate noise that result in overvoltage stress on devices. careful component placement layout and printed circuit design minimizes the voltage spikes induced in the converter. follow the layout guidelines for optimal performance of up6103 1 the upper and lower mosfets turn on/off and conduct pulsed current alternatively with high slew rate transition. any inductance in the switched current path generates a large voltage spike during the switching. the interconnecting wires indicated by red heavy lines conduct pulsed current with sharp transient and should be part of a ground or power plane in a printed circuit board to minimize the voltage spike. make all the connection the top layer with wide, copper filled areas. 2 place the power components as physically close as possible. 2.1 place the input capacitors, especially the high- frequency ceramic decoupling capacitors, directly to the drain of upper mosfet ad the source of the lower mosfet. to reduce the esr replace the single input capacitor with two parallel units 2.2 place the output capacitor between the converter and load. 3 place the up6103 near the upper and lower mosfets with pins 1 to 4 facing the power components. keep the components connected to pins 4 to 8 close to the up6103 and away from the inductor and other noise sources (noise sensitive components). 4 use a dedicated grounding plane and use vias to ground all critical components to this layer. the ground plane layer should not have any traces and it should be as close as possible to the layer with power mosfets. use an immediate via to connect the components to ground plane including gnd of up6103. use several bigger vias for power components. 5 apply another solid layer as a power plane and cut this plane into smaller islands of common voltage levels. the power plane should support the input power and output power nodes to maintain good voltage filtering and to keep power losses low. also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. 6 the phase node is subject to very high dv/dt voltages. stray capacitance between this island and the surrounding circuitry tend to induce current spike and capacitive noise coupling. keep the sensitive circuit away from the phase node and keep the pcb areasmall to limit the capacitive coupling. however, the pcb area should be kept moderate since it also acts as main heat convection path of the lower mosfet. 7 up6103 sources/sinks impulse current with 2a peak to turn on/off the upper and lower mosfets. the connecting trance between the controller and gate/ source of the mosfet should be wide and short to minimize the parasitic inductance along the traces. 8 flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power component. 9 provide local vcc decoupling between vcc and gnd pins. locate the capacitor, c boot as close as practical to the boot and phase pins.
upi semiconductor corp., http://www.upi-semi.com rev. f00, file name: up6103-ds-f0000 up6103 14 note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15mm. package informatio n 0.32 - 0.52 4.80 - 5.00 5.80 - 6.20 3.81 bsc 0.10 - 0.25 0.18 - 0.25 0.41 - 0.89 1.27 bsc 3.80 - 4.00 recommended solder pad layout 1.75 max 1.45 - 1.60 7.00 10 0. 1.50 10 0. 0.70 10 0. 1.27 10 0. 5.50 10 0. 4.00 10 0. sop - 8l
upi semiconductor corp., http://www.upi-semi.com rev. f00, file name: up6103-ds-f0000 up6103 15 package informatio n 0.32 - 0.52 4.80 - 5.00 5.80 - 6.20 0.18 - 0.25 0.40 - 0.90 7.00 10 0. 1.50 10 0. 0.70 10 0. 1.27 10 0. 1.27 bsc 3.80 - 4.00 5.50 10 0. 4.00 10 0. recommended solder pad layout 1.80 - 2.30 1.80 - 2.30 2.20 10 0. 2.20 10 0. 3.81 bsc 0.05 - 0.25 1.75 max 1.45 - 1.60 psop - 8l note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15mm.

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